PCB Design Rules

Syntax's for Clearance Rules

InPolygon

InNamedPolygon('L3 - 3V3')

(ObjectKind = 'Poly') And (Name like '*L05_GND*')

(OnLayer('L1 TOP') and InPolygon) 

(OnLayer('L1 - TOP'))

Not( OnLayer('L8 3V3/RF') OR OnLayer('L9 5V')) 

InNetClass('CPW')

InNet('RF_PORT') AND InComponent('X100') 

InNet('26MHz')

(InNet('RF_PORT') AND OnLayer('L1 - TOP'))

HasPad('J1400-1') OR HasPad('J1001-1')

InComponent('D1200')

Not (InComponent('TH100') Or InComponent('TH101')) 

(ObjectKind = '3D Body') And (Identifier = 'SOM') 

(AsMils(HoleDiameter) = 130)
(AsMM(HoleDiameter) = 3.3)

(AsMils(HoleDiameter) >= 8) 

(AsMM(HoleDiameter) >= 0.2) 

WithinRoom('DDR3_ROOM')

OnLayer('L1 TOP') or OnLayer('L16 BOT')      

IsPad

IsVia

Hole to Hole Clearance Rules

Thru-Hole Pin

IsThruPin
InPolygon
8mil

NPTH Rules

((HoleDiameter >= PadXSize_AllLayers ) OR (HoleDiameter >= PadYSize_AllLayers))

or use
(AsMM(HoleDiameter) > 0)   And (PadIsPlated = 'False')   

or use
(AsMil(HoleDiameter) > 0)   And (PadIsPlated = 'False')   

Routing Rules

Width

InNetClass('DDR_AC') or InNetClass('DDR_DQ') 

(ObjectKind = 'Track') And (Layer = 'L11-SIG') and InNetClass('MCP_ADDR[7..30]')

Differential Pair Rules

InNetClass('diff_80') 

InNetClass('diff_100') AND NOT withinroom('FPGA_ROOM') 

Component Clearance Rules

OnMechanical

InComponent('C1911') 

NOT InComponent('R1900') and NOT InComponent('C1904')       

InComponentClass ('Class_Name')

Negative values allow for overlapping parts

Hole to Hole Rules

InNet('GND') 

to 

InNet('GND')

 

Slots

HoleType = 'Slot'  


Net Antennae Rules

To Allow a Net Antennae

NOT (InNet('DXN_0_N') OR InNet('DXP_0_P')) 

InNet('NetF1100_1') and IsViolation   


Pads

InPadClass('Mtg_Holes')

(ObjectKind = 'Pad') And (Component = 'U2')


Soldermask Rules

Tent (Cover) Vias

isVia and (AsMM(HoleDiameter) < 0.4)

isVia and (AsMil(HoleDiameter) < 15)

Silkscreen To Solder Mask Clearance

First Object Matches 

isPad or IsRegion or isFill   

Second Object Matches

All

Clearance Checking Mode

Check Clearance to Solder Mask Openings

Silkscreen to Object Minimum Clearance 

Use 4 to 6 mils (0.1 to 0.15 mm) when using Zero Solder Mask Expansion

NPTH

(ObjectKind = 'Pad') And (AsMM(HoleDiameter) > 0)  And (PadIsPlated = 'False') 

Check Solder Mask from Hole Edge   
0.125mm


SMD Pads to Thru-Hole Solder

Find Vias In Pads and use Via soldermask encroachment.

Steps: 

Identify Vias in Pads using a DRC check. 

IsPad 

IsVia 

AnyNet

Minimum clearance 3mils

Select Components and Unlock Primitives.

Use PCB Filter isVia and HasViolations

Set selected Vias to unique hole size i.e. 8,01 or 10.1mils and use rule based soldermask.

Delete or disable the temporary DRC to find the Vias in Pads

Create a Solder mask expansion Rule for the unique drill hole sized vias.

IsVia AND (AsMils(HoleDiameter) = 8.01)  

IsVia AND (AsMM(HoleDiameter) = 0.2)  

Check Solder Mask From The Hole Edge

Set expansion i.e. 3 or 4 mils

Done !

That's it !