Release Checks

Backup Project :

Use Project > Project Packager to Create a Backup First ! 

Or Commit the if you are using Version Control.

Schematic: 

Run a Tools > Update From Libraries (for the whole design)

Make sure Schematic and PCB are in Sync

Project > Validate > Update PCB
Review Not Fitted Parts and Variants.

Project > Validate > Update PCB
Review Requested Changes and ECO Change Lists.
Review BOM for Fitted / Not Fitted Parts and Variant Part Numbers.

PCB:

Review all required electrical and mechanical design constraints.

Review return paths, look for signal traces crossing moats in GND pours.

Review all project outputs for Fabrication and Assembly.

Review Solder mask, Solder Paste and Silkscreen. Fix as needed.

Check Board Stackup for Proper Internal Layer Naming.

Check Board Fiducials, Markings PCB and PCA numbers.

Check Position of the Database Origin.

Check Fab Dwg - Notes, Dimensions, Drill Table, Stackup and Impedance Table.

Check Assembly Dwg - Notes and Dimensions.

Check for Antennae Nets (Vias and Tracks).

Check for Via Stubs if Applicable

Check for Return Path Vias (use DRC Checks)

Check for Components and Pads on Mechanical Layers.

Check for No-Net Copper (Vias, Track, Arc, Fills, Regions, etc. . . 

Execute Selection Filters and Check the Properties Panel for Selected Objects.

Note: All Fixes Should be Pushed to the Footprint Library.

Select Pads with No Paste Enabled 

Pads - Select  Pads with NO Solder Paste

(ObjectKind = 'Pad') And (PasteMaskEnabled <> 'True') And IsSMTPin

The selected PADs may Include Thermal Paddles with Windowed Paste.

The selected PADs may Include Fiducials, Fiducials should not have Paste.

Suggested solution for Windowed Paste and Fiducials is Paste Enabled with -100% Expansion.

Nothing should be selected after executing the PCB Filters shown below !

Tip: Zoom Out (Short Cut Keys VF) before executing each Filter.

Components - Select Components that are Not on Top and Bottom Layers

(ObjectKind = 'Component') and not OnOutside

Polarity Text Dots - Select Text Strings with Zero Height

(ObjectKind = 'Text') And (AsMM(TextHeight) < 0.01)

NPTH - Select NPTH Pads with Plated Enabled to Find Mistakes

((HoleDiameter >= PadXSize_AllLayers ) OR (HoleDiameter >= PadYSize_AllLayers)) And (PadIsPlated = 'True')  

Pads - Select Thru-Hole Pads that have Paste In Pin for Review 

(ObjectKind = 'Pad') and IsThruPin And (PasteMaskEnabled <> 'False') 

Pads - Select Pads with Excess Solder Paste for Review

IsSMTPin And (PasteMaskExpansionMode = 'Manual') And (AsMM(PasteMaskExpansion) > 0)

Tracks - Select Tracks with Exposed Copper for Review

(ObjectKind = 'Track') And (SolderMaskExpansionMode = 'Manual') And (AsMils(PasteMaskExpansion) = 0) and OnOutside

VIAs - Select Pads that are Not using Rule Based Soldermask Expansion

(ObjectKind = 'Via') And (SolderMaskExpansionMode <> 'From Rule')

(ObjectKind = 'Via') And (IPC4761ViaType <> 'None')

Find Stacked uVias

IsStackedVia

Regions - Select Free Regions with Exposed Copper for Review

(ObjectKind = 'Region') And (SolderMaskExpansionMode <> 'None') and OnOutside and Not InComponent('*') And (IsCutoutRegion = 'False')

Regions - Select Regions with 0 size Area.  These should be deleted.

(ObjectKind = 'Region') AND (Area='0 sq.inch')

Review selected Pad after executing the PCB Filters shown below !

Pads - Select Pads that are Not using Rule Based Soldermask Expansion

(ObjectKind = 'Pad') And (SolderMaskExpansionMode <> 'From Rule')

Paste in Pin (PIP) - ThuHole Pads with Solder Paste

IsThruPin And (PasteMaskEnabled = 'True')

Properties Panel > Select Pad Stack > Simple > Solder Paste > Enabled 

or

IsThruPin And (PasteMaskEnabled = 'False')

Properties Panel > Select Pad Stack > Simple > Solder Paste > Not Enabled 

Note: Thermal Pads and region may need to use Manual Expansion.

To Fix a Pads in a PCBDoc Select Components > Unlock Primitives

After executing a Filter use Find Similar and Properties Panel to make changes.

Solder Paste and Solder Mask - Examples for Pads:

Properties Panel > Select Pad Stack > Simple > Solder Paste > Enabled and Manual 

Properties Panel > Select Pad Stack > Simple > Solder Mask> Rule Expansion

Paste Mask and Solder Mask for Free Regions and Fills in PCBDoc:

Properties Panel > Select Pad Stack > Simple > Paste Shape > NOT Enabled

To Find Fills and Regions on Paste Layers (i.e. Thermal Paddles)

((ObjectKind = 'Region') And (Layer = 'TopPaste')) or ((ObjectKind = 'Fill') And (Layer = 'TopPaste')) or ((ObjectKind = 'Region') And (Layer = 'BottomPaste')) or ((ObjectKind = 'Fill') And (Layer = 'BottomPaste'))

Rememeber !  Select Components > Lock Primitives when done.

Useful Components and Designators Filters

Components - Select All Components Except Caps and Resistors

(ObjectKind = 'Component') And (Not(Name Like 'C*')) And (Not(Name Like 'R*'))

Components - Select All Components Except Caps, Resistors and Inductors

(ObjectKind = 'Component') And Not(Name Like 'C*') And Not(Name Like 'R*') And Not(Name Like 'L*')

Components - Select All Except Caps, Inductors, Resistors & Fiducials

(ObjectKind = 'Component') And Not(Name Like 'C*') And Not(Name Like 'R*') And Not(Name Like 'L*') And Not(Name Like 'FD*') And Not(Name Like 'FID*')

Components - Select Parts with Designators Like R* or C*

(ObjectKind = 'Component') And (Not(Name Like 'C*')) And (Not(Name Like 'R*'))

Designators - Select Designators with Silkscreen Violations

(ObjectKind = 'Text') And (StringType = 'Designator') And (Layer = 'TopOverlay') and HasViolations

Copper Cleanup

Stackup Folder - readme.txt file

Do not delete this file.

Refer to the Stackup in the Fab notes

If available a copy of an approved fabricator stackup may be placed in this folder.

That's it !

Solder Robbers

Altium's 3D board view is an excellent tool for identifying the root cause of soldering related problems.

Example:

The x-ray below shows a pad that has insufficient solder (see mouse pointer).

Lets look at this using Altium's 3D design viewer.

Right away I see a solder robber.  A trace was routed along side a pad, which created a larger area for the solder to flow across.

Fix: 

That's It !

DFM - Non Plated Hole - Soldermask FHS + 10mil

Design for Manufacturability (DFM) for Non Plated Thru Hole (NPTH) the soldermask opening should be finished hole size (FHS) + 10mils.

Example: NPTH for test fixture tooling, soldermask = FHS + 10mil (0.25mm)

In Altium this means the Soldermask expansion should be +5mils (0.125mm).

You should also include a copper keep out on all layers of FHS + 10mils.

There are no Design rules or DRCs in Altium for Non-Plated Thru Holes that will catch this DFM issue.

DFM - Soldermask Coverage

There are no design rules in Altium to identify the soldermask coverage problem described below. 

Note the soldermask shown below is too close to a different net. Standard soldermask registration accuracy is +/- 3mils (75um).

You need to use fabrication CAM tools to identify these errors or set your copper to copper rules with clearances that account for soldermask registration accuracy.

Source: High Volume Overseas Contract Manufacturer.

"Soldermask alignment capability exposes traces and features."

"Bridging during the assembly process may occur if the circuit features that pass close to pads are not fully covered by soldermask or potential corrosion problem if lack of coverage exposes copper."

Suggested Solution from Contract Manufacturer:

"Move the circuit features away from the pad or move the pad away from the circuit features. And if the soldermask clearance is large enough then reduce the soldermask clearance. If all of them can not be modified, soldermask encroach on pad should be allowed in lieu of allowing exposed copper feature."

My Comments and Solutions:

The DFM tolerance in the CAM tool for this violation was 2.953mil.  

In Altium the minimum copper to copper clearance for 'ALL'  different nets was 0.15mm (5.905mil). And the soldermask swell was set for 4mils. so the math works out to:

5.095 minus 4 = 1.905  (Copper to Copper minus Soldermask Swell = Coverage)

Copper to Copper Rule minus soldermask swell = soldermask coverage with perfect soldermask registration.

However the soldermask registration accuracy (+/- 3mil) needs to be considered for the outer layers which are covered with soldermask. 

To allow for soldermask registration accuracy of +/- 3mil we would need a minimum copper to copper clearance rule of 7mil.

7 minus 4 = 3mils (Copper to Copper minus Soldermask Swell = Coverage).

For standard LPI soldermask processes the copper to copper rules for the outer layers should be set to least 7mils, preferably 8mils.

For fine pitch parts with pin to pin clearances equal to or less than the minimum copper to copper rule clearance you can gang the soldermask and create rooms with appropriate clearance rules.

That's It.

Altium Script - Via Soldermask Barrel Relief

Updated Via Soldermask Barrel Relief (9-11-2013 11-24-56 AM)

PCB fabricators may request permission to apply Soldermask Barrel Reliefs to your tented vias when the via's hole sizes are 18mil or larger in size.  Consult with your fabricator as the requirements vary between suppliers.

For more about Soldermask Barrel Reliefs see : Via Barrel Reliefs - PCB Designer Blog 

Fabricators specify the barrel reliefs with respect to the via hole size. For example drill hole size + 5mil is typical.

The +5mil soldermask relief accounts for registration and process tolerances.

To Force Complete Tenting

Tenting vias on one side can trap chemicals and fluxes in the via barrels which can corrode away the copper plating in the via barrels. This is a reliability issue. 

Reference:  Soldermask on via-holes in case of chemical Nickel-Gold surface finish

Silkscreen to Soldermask Clearance Rules

AD13 Introduced Silkscreen to Soldermask Clearance Rules.

This library part has soldermask defined pads.

3D View

The clearance violations are due to the soldermask defined pads (where soldermask swell is less than the pad size) .


Out of the box rule shown below.

Click on image to view.

Work Around:

Check Clearance to Solder Mask Openings


And use:

(IsText OR IsTrack OR IsArc OR IsFill)
     
OnTopSolderMask Or OnBottomSolderMask 

As shown above I used a 3 mil Clearance rule. If the soldermask swell is 4 mil then this would be the same as a silkscreen to pad clearance rule of 7 mils.

That's It !

Soldermask Dots

I recently had a design  where I needed soldermask dots on a thermal pad as shown below. 

An experienced Altium user solved this problem using FILLs applied to the soldermask layer as shown below. The result is soldermask squares that tented the VIAs.

Single layer mode - 3D View of the Soldermask