Electra Design Rule - class_class

Example class to class rule for Electra

define (class_class (classes LV HV (rule (limit_way 2000))))

define (class_class (classes LV HV (rule (clearance 300 (type pin_pin)))))

define (class_class (classes LV HV (rule (clearance 300 (type pin_via)))))

define (class_class (classes LV HV (rule (clearance 300 (type pin_wire)))))

define (class_class (classes LV HV (rule (clearance 300 (type pin_smd)))))

define (class_class (classes LV HV (rule (clearance 300 (type pin_area)))))

define (class_class (classes LV HV (rule (clearance 300 (type via_via)))))

define (class_class (classes LV HV (rule (clearance 300 (type via_wire)))))

define (class_class (classes LV HV (rule (clearance 300 (type via_smd)))))

define (class_class (classes LV HV (rule (clearance 300 (type via_area)))))

define (class_class (classes LV HV (rule (clearance 300 (type wire_wire)))))

define (class_class (classes LV HV (rule (clearance 300 (type wire_smd)))))

define (class_class (classes LV HV (rule (clearance 300 (type wire_area)))))

define (class_class (classes LV HV (rule (clearance 300 (type smd_smd)))))

define (class_class (classes LV HV (rule (clearance 300 (type smd_area)))))

define (class_class (classes LV HV (rule (clearance 10 (type area_area)))))

define (class_class (classes LV HV (rule (clearance 5 (type smd_via_same_net)))))

Example class_class_layer

define (class_class (classes LV HV (layer_rule BottomLayer (clearance 150))))

Example for using high cost to minimize routing on a specific layer

cost layer LayerName high (type length)

That's it !

Electra Panels

Right Click on the Main Menu to pop open the panels dialog.

That's it !

Electra Do File Tweaks

To clear existing routed tracks and vias, except GND and Diff Pairs.

Altium > PCB Fliter

(IsTrack or isVia) and OnSignal and not InNet('GND') and not InAnyDifferentialPair

Delete Filtered Selection

Altium > Script > Export Specctra DSN

# My Do

select all nets
unselect net GND
unprotect all wires
unprotect all vias

lock net GND
protect net GND
protect all dpairs

print {Tax via 5 (high)}

reset

tax via 5

bestsave on "tax_via_5"

autoroute

report summary "tax via 5"

# End My Do 

Electra > Altium  

Electra

Run My Do

File > Export Routes 

Tip:

Do Not Assume any Existing *.rte files are good, always Export > Routes

Altium

File > Import Specctra Route

Design Netlist > Clean All Nets

Run DRC > Review and Fix as Needed

Altium PB Filters

Istrack and OnSignal and not InAnyDifferentialPair

(Istrack or IsArc or isVia) and OnSignal and not InAnyDifferentialPair and (Keepout = 'False') and not InNetClass('PWR')

Altium

Route > Retrace Selected (Shortcut Keys UC)

Tips: 

Altium

Preferences > PCB Editor > Gloss And Retrace > Miter Ratio 3

That's it !

Altium Export to Specctra and Electra

* Altium - Use Net Class Directives for Diff Pairs instead of Diff Pair Directives.

* Altium - Delete all Solid Polygons or use Hatched Polygons.

* Altium - Simplify the design rules, i.e. Clearance All 7mils and not InAnyDifferentialPair

* Altium - Simplify the design rules for trace width, i.e. 5mils

* Altium - Use only one drill size when exporting to Specctra

* Altium - Use only Thru-Hole and Blind Vias

* Altium - Copy the board outline to the Keepout layer to keep routes inside the borders.

* Altium - Export Specctra *.dsn file.

* Electra - Fanout GND Vias. Protect and then Unselect Net GND (Do Not Route GND)

* Electra - Run the Router and Export the the Routes.

* Altium - Import the Routes *.rte file.

* Altium - Run DRC Checks and Cleanup routes as needed.

* Altium - Clean up Diff Pairs using Find Similar and Retrace.

* Altium - Net Antennae Design Rule NOT ((ObjectKind = 'Via') And (Net = 'GND'))

Ensuring PCB Readiness for Specctra-compatible Routers in Altium Designer

Bugs and Tips:

https://forum.live.altium.com/#/posts/251575/797738

https://forum.live.altium.com/#/posts/254379/812665

That's it !