Tuesday, February 25, 2014
Signal Integrity Software, Inc | SiSoft
SiSoft Quantum-SI Export - Altium
Signal Integrity Software, Inc | SiSoft:
Please leave a comment if you have any experience with Altium > SiSoft.
'via Blog this'
Differential Pairs - Rules
In AD14 Differential Pairs width and gap rules are combined.
"Improvements to the differential pair rule definition, the ability to cycle the width-gap setting, and support for room-based rule scoping were added in Altium Designer 14."
Rule Definition for Differential Pair Routing - Altium
In AD14 Width and Gap are set up in a single rule.
In AD13 Width and Gap are set up using a Differential Pair rule and a Trace width rule.
AD13 Gap Rule for Differential Pair
AD13 Width rule for Differential Pair
Matched Length Rules are the same in AD13 or AD14.
Tip: For Forward and Backward compatibility you can leave the AD13 rules in a design and update the new AD14 Differential Pair Rule using the sittings found in the two AD13 rules.
"Improvements to the differential pair rule definition, the ability to cycle the width-gap setting, and support for room-based rule scoping were added in Altium Designer 14."
Rule Definition for Differential Pair Routing - Altium
In AD14 Width and Gap are set up in a single rule.
In AD13 Width and Gap are set up using a Differential Pair rule and a Trace width rule.
AD13 Gap Rule for Differential Pair
AD13 Width rule for Differential Pair
Matched Length Rules are the same in AD13 or AD14.
Tip: For Forward and Backward compatibility you can leave the AD13 rules in a design and update the new AD14 Differential Pair Rule using the sittings found in the two AD13 rules.
Monday, February 24, 2014
Pad | DOCUMENTATION - Altium Tech Docs
Pad | DOCUMENTATION: "Testpoint Settings"
PADs or VIAs can be nominated as Test Points.
Find and Set Testpoints can be used to select existing pads or vias.
'via Blog this'
PADs or VIAs can be nominated as Test Points.
Find and Set Testpoints can be used to select existing pads or vias.
'via Blog this'
Thursday, February 20, 2014
Drill Table - Panel.doc Issues
Drill tables are coming into the Panel.doc from single boards and these tables do not account for the additional holes in the Panel.doc for rat bites and slots.
If you have four PCBs in your Panel.doc you will end up with four drill tables, plus a fifth drill table if you place a drill table in your Panel.doc.
The Panel.doc drill table will account for all of the drills including any rat bites and slots.
The only solution I have found is to delete the drill tables on the individual PCBs and add a drill table to the Panel.doc.
Altium Bug Crunch #2059
Thursday, February 13, 2014
DDRx Routing Tips - Part 1
When routing DDRx with Altium you need to use some clever tricks or third party tools to get the job done.
Altium Bug Crunch #960: Altium Live Log in Required
Currently your options include:
When using net ties you should be prepared to get a notice from your fabricator that your design has shorted nets. To avoid an unexpected call you should identify the shorted nets in the design for your fabricator in a read me file.
"This type of component allows two (or more) nets to be connected together, for example a digital ground and an analog ground that must be connected at a specific location on the schematic and in the PCB routing. They are always synchronized to the PCB and are always included in the BOM. Use this Type of Net Tie if a jumper type component is to be fitted as part of the assembly process. When placing components of this Type, use the Verify Shorting Copper option in the Design Rule Checker dialog when performing a DRC in the PCB, to verify the short correctly exists."
Source: http://techdocs.altium.com/display/ADRR/Sch_Obj-Part((Part))_AD
Below is a two pin Net Tie that has been optimized for a DDRx project. This Net Tie is used instead of VIAs in the design to connect nets to termination resistors.
Schematic Symbol for a Net Tie with two pins.
Net Tie Footprint with two overlapping pads.
3D View of the above Net Tie
Example Routing
Note the net names for DDR3_A9_3 and DDR3_T_A9_3.
This removes the trace length of (DDR3_T_A9_3) for the termination connection from the net (DDR3_A9_3) leaving us with the Net length from the memory controller to the memory chip.
See Altium Addons for a nice library of Net Ties created by Petr Tosovsky.
Net-ties along with some clever routing tricks can improve the length data displayed in the PCB Panel.
Here is one example of a clever trick to simplify determining the Net length when you have a series resistor in the signal path.
By temporarily placing a short across a resistor in the schematic we can get the total Net length for a trace in the PCB Panel from the transmitting IC to the receiving IC.
Download Lib_NetTieLib
Track segments are selected along the path of interest, then the R, S keys are pressed to display the length of the selected trace segments.
Some users go to great lengths (that's was a pun) to verify every critical trace length manually. This can be done by entering measured Net data in a spreadsheet.
For an example of using measured Nets and a spreadsheet see:
To avoid seeing this message you may want to leave your polygons un-shelved (poured) and use the view option to hide the polygons while routing your board.
To use Hyperlynx refer to Mentor Graphics documentation.
Setting up and using Hyperlynx is WAY beyond the scope of this article.
DDR3 Routing - Simplified Part 1
DDR3 Routing - Simplified Part 2
Until next time.
Best regards,
Randy
Altium Bug Crunch #960: Altium Live Log in Required
Currently your options include:
- Using Net Ties.
- Manually measuring trace segments.
- Exporting nets to Hyperlynx.
- Use Net Length Tool.
Net Ties
Net ties are workarounds used by get better net length data from Altium.When using net ties you should be prepared to get a notice from your fabricator that your design has shorted nets. To avoid an unexpected call you should identify the shorted nets in the design for your fabricator in a read me file.
"This type of component allows two (or more) nets to be connected together, for example a digital ground and an analog ground that must be connected at a specific location on the schematic and in the PCB routing. They are always synchronized to the PCB and are always included in the BOM. Use this Type of Net Tie if a jumper type component is to be fitted as part of the assembly process. When placing components of this Type, use the Verify Shorting Copper option in the Design Rule Checker dialog when performing a DRC in the PCB, to verify the short correctly exists."
Source: http://techdocs.altium.com/display/ADRR/Sch_Obj-Part((Part))_AD
Below is a two pin Net Tie that has been optimized for a DDRx project. This Net Tie is used instead of VIAs in the design to connect nets to termination resistors.
Schematic Symbol for a Net Tie with two pins.
Net Tie Footprint with two overlapping pads.
3D View of the above Net Tie
Example Routing
Note the net names for DDR3_A9_3 and DDR3_T_A9_3.
This removes the trace length of (DDR3_T_A9_3) for the termination connection from the net (DDR3_A9_3) leaving us with the Net length from the memory controller to the memory chip.
See Altium Addons for a nice library of Net Ties created by Petr Tosovsky.
Net-ties along with some clever routing tricks can improve the length data displayed in the PCB Panel.
Here is one example of a clever trick to simplify determining the Net length when you have a series resistor in the signal path.
By temporarily placing a short across a resistor in the schematic we can get the total Net length for a trace in the PCB Panel from the transmitting IC to the receiving IC.
Download Lib_NetTieLib
Manual Measurements
To verify net length data displayed in the PCB panel users check trace lengths manually.Track segments are selected along the path of interest, then the R, S keys are pressed to display the length of the selected trace segments.
Some users go to great lengths (that's was a pun) to verify every critical trace length manually. This can be done by entering measured Net data in a spreadsheet.
For an example of using measured Nets and a spreadsheet see:
Export to Hyperlynx
When exporting a Hyperlynx file from later versions of Altium you will get an error message if you have shelved polygons in the design.
To avoid seeing this message you may want to leave your polygons un-shelved (poured) and use the view option to hide the polygons while routing your board.
To use Hyperlynx refer to Mentor Graphics documentation.
Setting up and using Hyperlynx is WAY beyond the scope of this article.
Related Links:
DDR3 Routing - Simplified Part 2
Until next time.
Best regards,
Randy
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