New in AD17.1.5

One of my projects has 3 Violations that did not exists in prior versions. 



2 of 3 violations are related keep outs and the other violation is a soldermask web near via.

Lucky for me Altium included a new feature in AD17.1.5 that allows for selectively waiving DRC violations. Waiving DRCs is useful for backward compatibility.

Selectively Waiving DRC Violations | Online Documentation for Altium Products

New in AD17.1.5
Altium Designer 17.1 is now available (15 May 2017)

That's it !

Short Circuit Rules

DRC's for Short Circuits.

Short Circuits violations can include unused pins of a fanned out BGA.

Or custom footprints that have two primitives with the same pin number.

Example Datasheet for the QFN shown above suggested using chamfered pads for the corner pins.


Two primitives were used to create chamfered pads, a top layer pad and a region.

Pads that are made up two or more primitives can cause Short Circuit DRCs if the pads have no nets assigned.

The solution is to create a Short Circuit rules to allow primitives with no assigned nets to overlap, using 'Not InAnyNet' 


Allow all No Nets to short together.

This same technique can be used to allow BGAs to be fanned out and pass the DRC checks for short circuits when the pins don't have assigned nets (No Nets).

For a BGA with unused fanned out connections.

Allow for overlapping primitives in the same part (not fanned out)

 

That's It !

Component Clearances - DRCs

DRCs for component to component clearances depend on what information Altium has to work with.

For example in the first screen shot below you can see there is DRC clearance error for U1000. 

When a part is selected in the 3D view the perimeter of the part and it's primitives are defined. 

The part perimeter includes the silkscreen (Overlay) layer when a component body is not included in the footprint.

In the example below the pin 1 character on the Top Overlay has defined the lower extent for the component (U1000).






















Altium uses extruded component bodies and step models if they are available when checking for component clearances.

After adding an extruded 3D body to U1000 and running the DRC check again the design passes the component to component clearance check.

Design Rules Reference

"This comprehensive reference provides detailed information on setting up design rules 
for a PCB design. It also covers addition of rule-based parameters to objects in the 
schematic and Design Rule Checking. Detailed information for each of the individual 
rule types and their associated constraints is also provided."

Source: Altium Design Rules Reference 

'via Blog this'

DRCs - Interrogating Violations - English documentation - The Altium Wiki

Interrogating Violations - English documentation - The Altium Wiki:

"There are essentially three methods of interrogating design violations - from the Messages panel, from the PCB panel and directly within the design workspace."

'via Blog this'

Silkscreen to Soldermask Clearance Rules

AD13 Introduced Silkscreen to Soldermask Clearance Rules.

This library part has soldermask defined pads.

3D View

The clearance violations are due to the soldermask defined pads (where soldermask swell is less than the pad size) .


Out of the box rule shown below.

Click on image to view.

Work Around:

Check Clearance to Solder Mask Openings


And use:

(IsText OR IsTrack OR IsArc OR IsFill)
     
OnTopSolderMask Or OnBottomSolderMask 

As shown above I used a 3 mil Clearance rule. If the soldermask swell is 4 mil then this would be the same as a silkscreen to pad clearance rule of 7 mils.

That's It !

Wish List for Altium

1.  Solder paste to solder paste clearance DRC.

Shown below is the solder paste on two adjacent pins of a 16-TSSOP (0.173", 4.40mm Width) IC.

As shown below the solder paste is 1:1 with the pad and has a 0.05mm  (~3mil)  soldermask pullback.

Copper to copper feature and paste to paste is  0.2mm (~8mil).

The paste stencil would have a very long a skinny (0.2mm) web separating the solder paste blocks. The stencil could be damaged by the squeegee as the paste is applied.

It would be nice if the tool included a minimum the paste to paste clearance check.

Neck Down InRegionRelative

Using InRegionRelative(X1,Y1,X2,Y2) to Resolve PCB DRCs for Net neck downs.

References:
TR0110 Query Language Reference.PDF (Page 144) 

InRegionRelative must be specified in mils (English Units).

DRC Errors before applying InRegionRelative Rules

Create Clearance Design Rule for Specific Regions and Class Names.

Example Syntax: InRegionRelative(1072,175,1225,290)

Set Priority High

No DRC Errors After applying InRegionRelative Rules

 

Schematic View with Parameter Set (Directive)

 

Class Name 50R with a Clearance Rule Define in the Schematic.