In development and being fixed ?
Better support for high speed designs such as DDRx.
Altium BugCrunch #960:
'via Blog this'
Showing posts with label DDR2. Show all posts
Showing posts with label DDR2. Show all posts
Tuesday, April 8, 2014
Thursday, February 13, 2014
DDRx Routing Tips - Part 1
When routing DDRx with Altium you need to use some clever tricks or third party tools to get the job done.
Altium Bug Crunch #960: Altium Live Log in Required
Currently your options include:
When using net ties you should be prepared to get a notice from your fabricator that your design has shorted nets. To avoid an unexpected call you should identify the shorted nets in the design for your fabricator in a read me file.
"This type of component allows two (or more) nets to be connected together, for example a digital ground and an analog ground that must be connected at a specific location on the schematic and in the PCB routing. They are always synchronized to the PCB and are always included in the BOM. Use this Type of Net Tie if a jumper type component is to be fitted as part of the assembly process. When placing components of this Type, use the Verify Shorting Copper option in the Design Rule Checker dialog when performing a DRC in the PCB, to verify the short correctly exists."
Source: http://techdocs.altium.com/display/ADRR/Sch_Obj-Part((Part))_AD
Below is a two pin Net Tie that has been optimized for a DDRx project. This Net Tie is used instead of VIAs in the design to connect nets to termination resistors.
Schematic Symbol for a Net Tie with two pins.
Net Tie Footprint with two overlapping pads.
3D View of the above Net Tie
Example Routing
Note the net names for DDR3_A9_3 and DDR3_T_A9_3.
This removes the trace length of (DDR3_T_A9_3) for the termination connection from the net (DDR3_A9_3) leaving us with the Net length from the memory controller to the memory chip.
See Altium Addons for a nice library of Net Ties created by Petr Tosovsky.
Net-ties along with some clever routing tricks can improve the length data displayed in the PCB Panel.
Here is one example of a clever trick to simplify determining the Net length when you have a series resistor in the signal path.
By temporarily placing a short across a resistor in the schematic we can get the total Net length for a trace in the PCB Panel from the transmitting IC to the receiving IC.
Download Lib_NetTieLib
Track segments are selected along the path of interest, then the R, S keys are pressed to display the length of the selected trace segments.
Some users go to great lengths (that's was a pun) to verify every critical trace length manually. This can be done by entering measured Net data in a spreadsheet.
For an example of using measured Nets and a spreadsheet see:
To avoid seeing this message you may want to leave your polygons un-shelved (poured) and use the view option to hide the polygons while routing your board.
To use Hyperlynx refer to Mentor Graphics documentation.
Setting up and using Hyperlynx is WAY beyond the scope of this article.
DDR3 Routing - Simplified Part 1
DDR3 Routing - Simplified Part 2
Until next time.
Best regards,
Randy
Altium Bug Crunch #960: Altium Live Log in Required
Currently your options include:
- Using Net Ties.
- Manually measuring trace segments.
- Exporting nets to Hyperlynx.
- Use Net Length Tool.
Net Ties
Net ties are workarounds used by get better net length data from Altium.When using net ties you should be prepared to get a notice from your fabricator that your design has shorted nets. To avoid an unexpected call you should identify the shorted nets in the design for your fabricator in a read me file.
"This type of component allows two (or more) nets to be connected together, for example a digital ground and an analog ground that must be connected at a specific location on the schematic and in the PCB routing. They are always synchronized to the PCB and are always included in the BOM. Use this Type of Net Tie if a jumper type component is to be fitted as part of the assembly process. When placing components of this Type, use the Verify Shorting Copper option in the Design Rule Checker dialog when performing a DRC in the PCB, to verify the short correctly exists."
Source: http://techdocs.altium.com/display/ADRR/Sch_Obj-Part((Part))_AD
Below is a two pin Net Tie that has been optimized for a DDRx project. This Net Tie is used instead of VIAs in the design to connect nets to termination resistors.
Schematic Symbol for a Net Tie with two pins.
Net Tie Footprint with two overlapping pads.
3D View of the above Net Tie
Example Routing
Note the net names for DDR3_A9_3 and DDR3_T_A9_3.
This removes the trace length of (DDR3_T_A9_3) for the termination connection from the net (DDR3_A9_3) leaving us with the Net length from the memory controller to the memory chip.
See Altium Addons for a nice library of Net Ties created by Petr Tosovsky.
Net-ties along with some clever routing tricks can improve the length data displayed in the PCB Panel.
Here is one example of a clever trick to simplify determining the Net length when you have a series resistor in the signal path.
By temporarily placing a short across a resistor in the schematic we can get the total Net length for a trace in the PCB Panel from the transmitting IC to the receiving IC.
Download Lib_NetTieLib
Manual Measurements
To verify net length data displayed in the PCB panel users check trace lengths manually.Track segments are selected along the path of interest, then the R, S keys are pressed to display the length of the selected trace segments.
Some users go to great lengths (that's was a pun) to verify every critical trace length manually. This can be done by entering measured Net data in a spreadsheet.
For an example of using measured Nets and a spreadsheet see:
Export to Hyperlynx
When exporting a Hyperlynx file from later versions of Altium you will get an error message if you have shelved polygons in the design.
To avoid seeing this message you may want to leave your polygons un-shelved (poured) and use the view option to hide the polygons while routing your board.
To use Hyperlynx refer to Mentor Graphics documentation.
Setting up and using Hyperlynx is WAY beyond the scope of this article.
Related Links:
DDR3 Routing - Simplified Part 2
Until next time.
Best regards,
Randy
Friday, September 13, 2013
Excel - Conditional Formatting for Matched Net Lengths
Below is an example of using Green / Red (Go / No-Go) Conditional Formatting in Excel for checking matched trace length requirements.
Example
Example
Saturday, January 12, 2013
DDR2 Layout Guidelines
Signal Groups
Recommended sequence for routing the DDR2 memory:
1. Route data
2. Route address/command
3. Route control
4. Route clocks
5. Route feedback
The data group is routed first because it operates at twice the clock speed and its signal integrity is the highest priority. The data group represents the largest number of traces within the memory bus and has the strictest trace matching requirements.
The address, command and control lines have a relationship to the clock. The effective clock length needs to equal to the longest route within this group.
The designer should perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied.
Source Freescale AN2910:
Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces
DDR2 Differential Clock
DDR2 features differential clock inputs (CK and CK#). This differential clock is used to capture command and address, the nominal length is related to the address/command group.
Differential clocks lines should be routed to achieve the target differential impedance. Routing signals differentially reduces the flight time of the clocks compared to the single-ended signals. DDR2 design guides recommend that this clock signal be routed at the same length or slightly longer than the address, control and command signals to compensate for this single-ended / differential timing variation.
Source EET Asia:
DRR2 - Get it Right the First Time
Recommended sequence for routing the DDR2 memory:
1. Route data
2. Route address/command
3. Route control
4. Route clocks
5. Route feedback
The data group is routed first because it operates at twice the clock speed and its signal integrity is the highest priority. The data group represents the largest number of traces within the memory bus and has the strictest trace matching requirements.
The address, command and control lines have a relationship to the clock. The effective clock length needs to equal to the longest route within this group.
The designer should perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied.
Source Freescale AN2910:
Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces
DDR2 Differential Clock
DDR2 features differential clock inputs (CK and CK#). This differential clock is used to capture command and address, the nominal length is related to the address/command group.
Differential clocks lines should be routed to achieve the target differential impedance. Routing signals differentially reduces the flight time of the clocks compared to the single-ended signals. DDR2 design guides recommend that this clock signal be routed at the same length or slightly longer than the address, control and command signals to compensate for this single-ended / differential timing variation.
Source EET Asia:
DRR2 - Get it Right the First Time
Thursday, January 10, 2013
Saturday, November 10, 2012
Altium Designer - UK Experts - Microdex
Source: Altium Designer - UK Experts - Microdex - Tips
Tip #1
"Routing a bus with matched length? Use the altium designer PCB panel and select the bus class and sort the nets by length. Route the net with the largest man-hatten length first."
Tip #2
"For better EMC grounding scheme considering defining net ties to make your GND star points."
Tip #3
"If you need to match track lengths for a whole bus including strobe / control signals, within altium designer use a harness on the schematic, this will create a complete net class of the group."
Tip #1
"Routing a bus with matched length? Use the altium designer PCB panel and select the bus class and sort the nets by length. Route the net with the largest man-hatten length first."
Tip #2
"For better EMC grounding scheme considering defining net ties to make your GND star points."
Tip #3
"If you need to match track lengths for a whole bus including strobe / control signals, within altium designer use a harness on the schematic, this will create a complete net class of the group."
Sunday, November 4, 2012
Design DDR, DDR2 & DDR3 - Barry Olney
PCB DESIGN 007 PCB Design Techniques for DDR, DDR2 & DDR3, Part 1:
PCB DESIGN 007 PCB Design Techniques for DDR, DDR2 & DDR3, Part 2:
"Crosstalk is quite common in high speed designs because of the cramped real estate; signals have to be packed tightly into a small area. Crosstalk can be minimized by increasing trace spacing and by reducing the signal layer to reference plane separation. Try to keep prepreg thickness to 3 MIL to tightly couple the signals to the plane. Also, it may be necessary to add additional planes to the stackup to isolate the offending aggressor signals. Routing adjacent signal layers orthogonally also helps reduce noise coupling."
Source: Barry Olney
PCB DESIGN 007 PCB Design Techniques for DDR, DDR2 & DDR3, Part 2:
"Crosstalk is quite common in high speed designs because of the cramped real estate; signals have to be packed tightly into a small area. Crosstalk can be minimized by increasing trace spacing and by reducing the signal layer to reference plane separation. Try to keep prepreg thickness to 3 MIL to tightly couple the signals to the plane. Also, it may be necessary to add additional planes to the stackup to isolate the offending aggressor signals. Routing adjacent signal layers orthogonally also helps reduce noise coupling."
Source: Barry Olney
Friday, November 2, 2012
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