DDR2 Layout Guidelines

Signal Groups

Recommended sequence for routing the DDR2 memory:

1. Route data
2. Route address/command
3. Route control
4. Route clocks
5. Route feedback

The data group is routed first because it operates at twice the clock speed and its signal integrity is the highest priority. The data group represents the largest number of traces within the memory bus and has the strictest trace matching requirements.

The address, command and control lines  have a relationship to the clock. The effective clock length needs to equal to the longest route within this group. 

The designer should perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied. 

Source Freescale AN2910: 
Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces


DDR2 Differential Clock

DDR2 features differential clock inputs (CK and CK#). This differential clock is used to capture command and address, the nominal length is related to the address/command group. 

Differential clocks lines should be routed to achieve the target differential impedance. Routing signals differentially reduces the flight time of the clocks  compared to the single-ended signals. DDR2 design guides recommend that this clock signal be routed at the same length or slightly longer than the address, control and command signals to compensate for this single-ended / differential timing variation.

Source EET Asia:
DRR2 - Get it Right the First Time