Typical designs have through hole pins for headers and connectors.
What is often overlooked is additional clearance needed to create the specified finished hole size (FHS) for pins that pass through the planes.
Design rules can be used to increase the anti-pad (copper clearance) that surrounds each pin that passes through a plane.
Example feedback from PCB fabricator:
The 43 mil holes are drilled at 47.2 mil and 59 mil holes are drilled at 63 mil to achieve the specified finished hole size after plating. After drilling the holes are 6 mils away from copper.
Can we increase the hole edge to copper spacing to prevent CAF issue ?
Problem:
The design is using a global minimum Plane Clearance rule (8mil).
The global minimum of 8 mils is adequate for small vias and tracks. However additional clearance is needed for through hole pins to prevent Conductive Anodic Filaments (CAF).
Solution:
Use design rules to increase the copper clearances for pins that pass through plane layers.
Through hole pins with 12 mil clearance.
That's It !
AD16 has options to use Drill Pairs for hole to hole clearances.
Click on images to view
In AD16.0.6 the drill pair rules are not working properly. Hole to Hole Clearance violations are not properly reported.
Also there are backward compatibility issues with using the drill pairs in AD16, they are not recognized in earlier versions of Altium.
When the DRC check is run in an earlier version you will get this error message.
Select Cancel.
Workaround for hole to hole clearance checks.
The solution shown below works and is backward and forward compatible.
Example 1: The rule shown below will catch both same net and different net hole to hole violations for holes greater than or equal to 6 mils in diameter.
(AsMils(HoleDiameter) >= 6)
Example 2: The rule shown below will catch both same net and different net hole to hole violations for any hole less than 6 mil in diameter.
(AsMils(HoleDiameter) < 6)
Example 3: Via to Via Clearance Rule,
The edge of hole to edge of hole distance will be determined by the clearance rule and the annular ring sizes of the adjacent vias.
For 8/18 vias use 5mil via to via clearances to create Hole to Hole 15mil clearances.
Any Net was selected to apply the rule to both same and different nets.
That's It !
By downloading and using these Sunstone specific rule sets you can have confidence that your board can be built by Sunstone without manufacturing difficulties or unnecessary delays.
Altium PCB Design Rules:
'via Blog this'
- Minimum feature size (web) 3 mil
- Minimum swell (soldermask expansion for pads) +2 mil
- Soldermask registration accuracy +/-1 mil or +/- 1.5 mil
- Check with your fabricator !
- Minimum Height 25 mil
- Minimum Line Width 4 mil
- Registration Accuracy +/-4mil
- Check with your fabricator !
Here's an interesting Broken Net error reported by a fabricator using an ODB++ file generated by Altium.
The DRC checks in Altium found NO opens (Broken Nets)
Examining Net_C401-1 shows where the problem lies:
As shown above NetC401-1 is passing across the pad of a capacitor, however there is not a connection dot in the pad.
To fix this problem we need to create separate connecting segments along the net to each pad.
There are no checks currently built into in Altium to find this reported error.
Design for Manufacturability (DFM) for Non Plated Thru Hole (NPTH) the soldermask opening should be finished hole size (FHS) + 10mils.
Example: NPTH for test fixture tooling, soldermask = FHS + 10mil (0.25mm)
In Altium this means the Soldermask expansion should be +5mils (0.125mm).
You should also include a copper keep out on all layers of FHS + 10mils.
There are no Design rules or DRCs in Altium for Non-Plated Thru Holes that will catch this DFM issue.
There are no design rules in Altium to identify the soldermask coverage problem described below.
Note the soldermask shown below is too close to a different net. Standard soldermask registration accuracy is +/- 3mils (75um).
You need to use fabrication CAM tools to identify these errors or set your copper to copper rules with clearances that account for soldermask registration accuracy.
Source: High Volume Overseas Contract Manufacturer.
"Soldermask alignment capability exposes traces and features."
"Bridging during the assembly process may occur if the circuit features that pass close to pads are not fully covered by soldermask or potential corrosion problem if lack of coverage exposes copper."
Suggested Solution from Contract Manufacturer:
"Move the circuit features away from the pad or move the pad away from the circuit features. And if the soldermask clearance is large enough then reduce the soldermask clearance. If all of them can not be modified, soldermask encroach on pad should be allowed in lieu of allowing exposed copper feature."
My Comments and Solutions:
The DFM tolerance in the CAM tool for this violation was 2.953mil.
In Altium the minimum copper to copper clearance for 'ALL' different nets was 0.15mm (5.905mil). And the soldermask swell was set for 4mils. so the math works out to:
5.095 minus 4 = 1.905 (Copper to Copper minus Soldermask Swell = Coverage)
Copper to Copper Rule minus soldermask swell = soldermask coverage with perfect soldermask registration.
However the soldermask registration accuracy (+/- 3mil) needs to be considered for the outer layers which are covered with soldermask.
To allow for soldermask registration accuracy of +/- 3mil we would need a minimum copper to copper clearance rule of 7mil.
7 minus 4 = 3mils (Copper to Copper minus Soldermask Swell = Coverage).
For standard LPI soldermask processes the copper to copper rules for the outer layers should be set to least 7mils, preferably 8mils.
For fine pitch parts with pin to pin clearances equal to or less than the minimum copper to copper rule clearance you can gang the soldermask and create rooms with appropriate clearance rules.
That's It.
"In PCB fabrication process, a copper sliver can cause material to detach during photo-imaging processes in fabrication. Floating pieces can cause defects and shorts which reduce yield. In electric performance aspect, slivers can even contribute to inconsistent impedance if they exist on a plane layer."
Source: High Volume Overseas Contract Manufacturer
My Comments:
Where is the sliver? I only see is a small gap in a copper poured plane or polygon.
To understand this DFM error you have to consider the copper photo-imaging process tolerances.
There are no DFM checks in Altium to identify copper laminate slivers, you need to use fabrication CAM and DFM tools to locate these laminate slivers in your designs.
The minimum gap allowed is 4mils.
