Design DDR, DDR2 & DDR3 - Barry Olney

PCB DESIGN 007 PCB Design Techniques for DDR, DDR2 & DDR3, Part 1:

PCB DESIGN 007 PCB Design Techniques for DDR, DDR2 & DDR3, Part 2: 

"Crosstalk is quite common in high speed designs because of the cramped real estate; signals have to be packed tightly into a small area. Crosstalk can be minimized by increasing trace spacing and by reducing the signal layer to reference plane separation. Try to keep prepreg thickness to 3 MIL to tightly couple the signals to the plane. Also, it may be necessary to add additional planes to the stackup to isolate the offending aggressor signals. Routing adjacent signal layers orthogonally also helps reduce noise coupling."

Source: Barry Olney