Friday, June 16, 2017

High Voltage - Explicit Design Rules

Outer Layer Rule "HV to LV :


For Designs with NO Inner Layer Vias (uVias or Buried Vias)

Example:  For Designs with Only Thru-Hole and Blind Vias use this Outer Layer Rule .

Scope1 Expression
InNetClass('HV') And Not OnMid

Scope2 Expression
InNetClass('LV') And Not OnMid

For Designs with Inner Layer Vias use ExistsOnLayer in your Scope.

Scope1 Expression
InNetClass('HV') And (ExistsOnLayer('Top Layer') Or ExistsOnLayer('Bottom Layer'))

Scope2 Expression
InNetClass('LV') And (ExistsOnLayer('Top Layer') Or ExistsOnLayer('Bottom Layer'))  

MId Layer Rule HV to LV :


Scope1 Expression
InNetClass('HV') 

Scope2 Expression
InNetClass('LV')

Notes:

When using ExistsOnLayer the Top Layer and Bottom layer names must match the user defined long layer names in the stackup.

As of AD25 and older versions ExistsOnLayer is the only reliable solution for designs  with Inner Layer Vias (Stacked uVias or Buried Vias) that use clearance and creepage rules.  Skip Vias are also affected.

Tips: Best Practice when using ExistsOnLayer 

For designs using ExistsOnLayer in the Stackup Designer always use Altium's default long layer names Top Layer and Bottom Layer.

Why ?  Because the design rules will be broken if the layer count or layer names change.


Bad Practice













Good Practice













Outer Layer Rules Must Have Higher Priority

That's it !