Tuesday, January 27, 2026

Altium Develop - Updates

Altium Develop updates are supported in the Preferences


 

Tuesday, October 7, 2025

Thursday, October 2, 2025

Ethernet Magnetics

Regarding the area under the magnetics (transformer)

https://g.co/gemini/share/83c46504add6  - Gemini AI (Copper Keepout)

1GB Ethernet Length Matching Requirements  - Gemini AI

That's it !

Wednesday, July 2, 2025

Tuesday, January 28, 2025

Via Stubs and Propagation Delay Script

Via Stubs and Delay - GUI

The Script can find Via Stubs and Set Via Propagation Delay.

Enter the Max Stub length allowed in mils. 

Select Top, Bottom or both to Find and Select Stubs.

Enter the desired max Via Stub length.

Double Clicking Max Stub will set Max Stub = to 1/2 Board's Copper Height.

For zero length stubs enter 0 in Max Stub.

Then select Run.

The script unshelves and repours polygons then starts checking the vias.

Store and Recall Buttons may be used to save and recall selected Via Stubs.

End or Via Stubs.

Via Propagation Delay Notes:

Select more or less than 1 Via to set the Propagation Delay of all Via Drill Pairs.
Select only one Via to set the Propagation Delay of all Via's in the same Drill Pair.
Click the Delay Button to update the Propagation Delay.

Note Altium calculates the delay as the proportion of the via the signal path between the start and stop layers, this is not the physical ength of the via. It is the signal path electrical length.

Example: A board with a total thickness of 61.8mil, including a total of 1mil of solder mask and 2mil outer Cu thickness, where the electrical via length is calculated as Total - Soldermask - 1/2 top Cu - 1/2 bot Cu = 58.8mil.  

Altium uses 1/2 of the copper height of the starting and stopping layers.

Example:

The Calculated Delay of the Via is 10.917pSec for a signal path length of 58.8mils.

Related Links:

Signal Integrity Characterization of Via Stubs on High-Speed DDR4 Channels | 2020-05-14 | Signal Integrity Journal

https://resources.altium.com/p/your-complete-guide-stub-analysis

For more inforamation about this script Contact Parts (Randy Clemmons)

That's it !

Thursday, January 16, 2025

Supply Nets (Voltage = 0 . . .

To disable Auto Generate Supply Nets

Preferences > General > Advanced > Schematic.AutoGenerateSupplyNetsRule > Disable

Restart (Close and Open) Altium

See: https://forum.live.altium.com/#/posts/260254/848610

That's it !

Saturday, January 11, 2025

Return Path Design Rules - DRC Gotchas

The Design Rule

Note:  

Most designs should NOT include Not inAnyDifferentialPair in the Scope as shown.

This is a special case for the board used in this Return Path DRC feature review.

The example Rule shown above is targeting a specific Net Classes i.e. IS0. and S50

You may want to set the Scope to target All.

Gotcha 1

In Gotcha 1 the problem is the GND Via on the left has a signal routed between the flagged via and the GND Via.

Solution 1: Add another Via or Waive the Violation

Other Points of Interest:

Per online help

Exclude small areas of copper from flagging a violation by setting the required value (in sq. mils, 10 by default) of the PCB.Rules.ReturnPathIgnoreArea option in the Advanced Settings dialog.

That's it !


Monday, September 16, 2024

90 Degree Routing - Glossing Off

Glossing must be OFF to simplify creating 90 Degree Corners



Saturday, September 14, 2024

Ethernet PHY - Length Matching

Ethernet PHY PCB Design Layout Checklist

The total length of each MDI trace should be less than 2 inches, or 2000 mils

The traces should be lengthmatched within 20 mils for 1G transmissions and within 50 mils for 100M or 10M transmissions. 

The number of vias and stubs on the MDI traces should be kept to a minimum.

The traces should be length- matched within  . . . 

20 mils for 1G transmissions

50 mils for 100M or 10M transmissions.

Also see Gemini AI: https://g.co/gemini/share/ee650e8e10c5

That's it !

ISSI SRAM/SDRAM Layout Guide

 See . . . 

AN42S01.AN - ISSI SRAM/SDRAM Layout Guide

ISSI - Integrated Silicon Solution Inc.
https://www.issi.com › pdf › appnotes › dram › AN...

Using SDRAM vs. DDR RAM in Your PCB Design | Blog | Altium Designer


ISSI DDR3 SDRAM Layout Guidelines (Download PDF)

Tuesday, May 7, 2024

Nine Dot Connects - Library Services

If you are looking for professional Altium Library design services and have a budget that can support the service then I highly recommend taking a look at  . . . 

Nine Dot Connects  -  Library Services

If you have a limited budget and like to do things yourself then I recommend you take Parts for free test drive. 

Link to Parts https://pcbparts.blogspot.com/p/welcome.html

Parts is a Scalable Database Library Managment Solution for Altium users.

Parts can be used to quickly create and manage an Access or MySQL Database Library.

To request technical support or a Free Parts online demonstration contact me at Parts.

Link: Contact Parts


Thank you for your support
Randy Clemmons

Routing Options - Explained

Interactive Routing Options - Online Altium (Login Required)

Gloss Effort (Routed) and Gloss Effort (Neighbor). 

You may think of Gloss as a postprocessor: after the trace is put in and conflicts resolved, it straightens the result to get rid of corners and other uglies. 

If it is Off, uglies are preserved, if Weak - the geometry of the trace mainly preserved, just locally smoothed, if Strong - the trace is made pretty much as short as possible.

See the pictures. Thin white line in all cases shows the trace as it was initially put in, then
the first picture shows how it came out after conflict resolution, Gloss (Routed) Off

the second - removed sharp corners and small jogs, Gloss (Routed) Weak

the third - tightened it, Gloss (Routed) Strong.


In addition to this, notice that not only the trace being routed may need improvement after conflict resolution, but also its neighbors, if they got pushed:

Again, the same three levels of Glossing are possible, and that is controlled By Gloss Effort (Neighbor) setting.

Automatically Terminate Routing

This is a small option. It controls what happens when during routing you click on a target to complete a connection. 

The trace to make the connection will be put in regardless of the setting, but after that you will either stay in the Routing command, so further cursor movements will put in more tracks, (Auto Terminate Off), or exit the command, so you can use the cursor to select the start point for the next trace (Auto Terminate On).


Pad Entry Stability

Controls Pad Entry, which is also the responsibility of Gloss (no Pad Entry if Gloss (Routed) is Off)

In this picture you see the thin white line showing the trace that was originally put in, and the final result, where Gloss improved the pad entry.

You may not think much of this improvement, but consider also these two cases:
 

Here keeping the middle entry caused a nasty acute angle at pad edge, and shifting it to the side is probably welcome.

So, Pad Entry Stability setting tells Gloss how close the corner has to be to the pad edge when shifting entry sideways becomes allowed. 

At Max it will never shift the entry, and you will get those acutes; at Off it will always shift, and you will always get off-center entry.

You may want to experiment with intermediate values to see which suites you, but be warned that picking different values near Off and near Max will result in pretty much the same behavior. 

I would recommend making the choice between Off, Max, and a couple of positions in the middle.

Added Clearance Ratio

This is related to Trace Centering option. 

This option works in an indirect manner: it tries to maintain some extra clearance to the obstacles. 

If the trace cannot squeeze between the obstacles, the extra clearance will be reduced by the same amount from both sides, so the trace will be centered between these obstacles. 

Otherwise the trace will be put at (normal + additional) clearance from obstacles, so in this case it will be not so much "trace centering" as "preferred clearance".


The value of the additional clearance, is controlled by Added Clearance Ratio. 

If the ratio is 1, then additional clearance equals the clearance from the rule, so the router will try try to maintain twice the normal clearance to the obstacles. 

The larger the ratio, the harder the router's job will be, and it is not recommended to go much beyond 2.


Miter Ratio

Consider the case when after a click while routing, you make a sharp turn.

Not everyone likes to have those right angles in their traces, which is when the miters come to the rescue - also the responsibility of Gloss.

Here the white thin line starts from the click point, but as you can see, a small portion of the previously committed trace is cut off and a short diagonal segment is inserted. 

That's a miter. You can also see miters if you scroll back to the picture demonstrating Weak Gloss. 

Miter Ratio controls the length of the miters used by the router. Since miters can be arcs as well as segments, they are defined in terms of "sharpest turn radius" as a multiple of trace width.

Miter Ratio 1 allows the radius equal to trace width, which can be plainly seen for arcs:

and not so plainly, but still true, for tracks:

Thursday, May 2, 2024

Back Drill

Design > Layer Stack Manager > Menu Back Drills


Select +Add > Properties Panel > Select First and Last Layer


Save Stackup to PCB

Design > NetClass > i.e. BackDrill > Add Nets

Design > Rules > High Speed > Max Via Stub Length


Select Net Class > BackDrill
Set Max Stub Length
Set Back Drill OverSize

Apply

Tools > Remove UnUsed Pad Shapes..


Repour Polygons and Review the Back Drills in 2D and 3D.

That's it !

Saturday, April 20, 2024

0.5mil Length Matched Diff Pairs

Customer's Requirements for 0.5mil Length matched Signals within the pairs.


Example
Sawtooth settings based on 6mil / 6mil (trace / gap) Diff Pair

Tip:

You have to select the type of tuning before you start tuning a net. 

Hit Tab Key before you start the length matching

Thank you Wayne :)

Saturday, February 17, 2024

Find and Fix Corrupt Mid Layers

Example six layer board with Corrupted Mid Layer IDs.

.Layer_ID  and .Layer_Name

Example . . . Corrupt Mid Layer IDs

The Fix . . .

Backup the Project Design Files using Project > Project Packager

Open the PcbDoc . . .

Import Changes from Project to Update the Netlist and Design Rules in the PcbDoc.

Run DRC checks, take note of any reported errors.

Create and open a Copy of the PcbDoc in the project.

Design > Layer Stack Manager

Export Stackup as CSV, then include Impedance Screen Captures in Excel.

Delete all Mid Layers from the Corrupt Stackup.

Then add Mid Layers as needed.

Save Stackup to the PcbDoc, then check Mid Layer IDs and Layer Names.

Example Corrected Mid Layer IDs.

Design > Layer Stack Manager

Enter Material Thickness and Impedances as needed.

Save the fixed Stackup to the copy of the PcbDoc 

Copy each Mid Layer from Original PcbDoc to Copy of PcbDoc.

Suggested Selection Filter Settings for Copying Mid Layers

Show all Mid Layers and use Signal Layer Mode.

Hide the Multi-Layer to avoid Selecting the Board and Board Cutouts.

Copy each Mid Layer from the Original PcbDoc to Copy of PcbDoc.

Use Edit > Paste Special > Check Paste on Current Layer and Keep Net Name.

Edit Design Rules and Fix Trace Width Rules as needed, including Diff Pairs.

Import Changes from Project to update the Netlist and Design Rules in the Copy.

Run DRC checks, take note of any reported errors.

Done !