PCB Design Best Practices - Mike Creeden

Routing Techniques In Altium Designer

PowerPoint Presentation

That's it !

IPC - Plated Mechanically Drilled Holes

 IPC Rule for Land Sizes for a Plated Mechanically Drilled Hole - Summit Interconnect

FPGA - Pin Mapper

Working with the FPGA Pin Mapper in Altium Designer - Altium Docs

For Xilinx Vivado® 2017.4:

Open the implemented design in Vivado.

Select File » Export » Export I/O Ports.

In the Export I/O Ports dialog, specify csv as type of I/O port to generate, and click OK.

To Export from Altium > Right Click on FPGA > Select Pin Mapping > Export

That's It !

Electra Design Rule - class_class

Example class to class rule for Electra

define (class_class (classes LV HV (rule (limit_way 2000))))

define (class_class (classes LV HV (rule (clearance 300 (type pin_pin)))))

define (class_class (classes LV HV (rule (clearance 300 (type pin_via)))))

define (class_class (classes LV HV (rule (clearance 300 (type pin_wire)))))

define (class_class (classes LV HV (rule (clearance 300 (type pin_smd)))))

define (class_class (classes LV HV (rule (clearance 300 (type pin_area)))))

define (class_class (classes LV HV (rule (clearance 300 (type via_via)))))

define (class_class (classes LV HV (rule (clearance 300 (type via_wire)))))

define (class_class (classes LV HV (rule (clearance 300 (type via_smd)))))

define (class_class (classes LV HV (rule (clearance 300 (type via_area)))))

define (class_class (classes LV HV (rule (clearance 300 (type wire_wire)))))

define (class_class (classes LV HV (rule (clearance 300 (type wire_smd)))))

define (class_class (classes LV HV (rule (clearance 300 (type wire_area)))))

define (class_class (classes LV HV (rule (clearance 300 (type smd_smd)))))

define (class_class (classes LV HV (rule (clearance 300 (type smd_area)))))

define (class_class (classes LV HV (rule (clearance 10 (type area_area)))))

define (class_class (classes LV HV (rule (clearance 5 (type smd_via_same_net)))))

Example class_class_layer

define (class_class (classes LV HV (layer_rule BottomLayer (clearance 150))))

Example for using high cost to minimize routing on a specific layer

cost layer LayerName high (type length)

That's it !

This object is part of a locked union. Continue?

 click on image to view

This message occurs while trying to move a union if primitives are locked in footprints in the union.

To avoid this popup all primitives in the footprints in the union need to be unlocked in each footprint library.

That's it !