Back Drilling Vias

Interesting Links . . .

Back drill vias - Altium Discussion Forums

Via Propagation Delay Notes

Interesting Links . . . 

Via Delay - Is it really a manual intervention - Altium Discussion Forums

PCB Design Best Practices - Mike Creeden

Routing Techniques In Altium Designer

PowerPoint Presentation

That's it !

IPC - Plated Mechanically Drilled Holes

 IPC Rule for Land Sizes for a Plated Mechanically Drilled Hole - Summit Interconnect

FPGA - Pin Mapper

Working with the FPGA Pin Mapper in Altium Designer - Altium Docs

For Xilinx Vivado® 2017.4:

Open the implemented design in Vivado.

Select File » Export » Export I/O Ports.

In the Export I/O Ports dialog, specify csv as type of I/O port to generate, and click OK.

To Export from Altium > Right Click on FPGA > Select Pin Mapping > Export

That's It !