Ideas for Altium

DRC Checks for Footprint Libraries

I would like to check footprints for DRCs i.e. soldermask and silkscreen for clearances as I make footprints.

Currently you have to place a part in a design then run DRCs to determine if the footprint has DRCs violations.

We need DRC rules that are specific to library parts that can be run as we create footprints.

View idea: http://bugcrunch.live.altium.com/#Idea/4192

Convert planes to Polygons

Using planes is great until you need better control of the copper pours. 

It would be great if we could Select a Plane Layer and convert all of the split planes on the layer to Polygons.

We could start a design and enjoy the speed and simplicity of using planes, including controlled impedance. 

Then as the design nears completion convert the Planes to Polygons to get the benefit of the smart copper rules that can be applied to Polygons.

View Idea: http://bugcrunch.live.altium.com/#Idea/4202?msgID=10320554

Convert Stitching VIAs to Free VIAs

Using Stitching Vias has been a painful experience for me. 

This is primarily due to the union which is automatically created. When I move a stitching via several other associated vias are moving and creating DRCs and breaking previously good routes.

Please give us an option to convert the stitching vias to free vias and break the stitching via unions.

View Idea: http://bugcrunch.live.altium.com/#Idea/4211?msgID=10357065

Solder paste to solder paste clearance DRC

Shown below is the solder paste on two adjacent pins of a 16-TSSOP (0.173", 4.40mm Width) IC.

As shown below the solder paste is 1:1 with the pad and has a 0.05mm  (~3mil)  soldermask pullback.

Copper to copper feature and paste to paste is  0.2mm (~8mil).

The paste stencil would have a very long a skinny (0.2mm) web separating the solder paste blocks. The stencil could be damaged by the squeegee as the paste is applied.

It would be nice if the tool included a minimum the paste to paste clearance check.