Friday, January 25, 2013
Monday, January 14, 2013
Footprint Tutorial - YouTube
Good tips for using the paste array feature and the insert key for a temporary origin.
Altium Designer Tutorial: Create a component library - YouTube
Altium Designer Tutorial: Create a component library - YouTube
Saturday, January 12, 2013
DDR2 Layout Guidelines
Signal Groups
Recommended sequence for routing the DDR2 memory:
1. Route data
2. Route address/command
3. Route control
4. Route clocks
5. Route feedback
The data group is routed first because it operates at twice the clock speed and its signal integrity is the highest priority. The data group represents the largest number of traces within the memory bus and has the strictest trace matching requirements.
The address, command and control lines have a relationship to the clock. The effective clock length needs to equal to the longest route within this group.
The designer should perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied.
Source Freescale AN2910:
Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces
DDR2 Differential Clock
DDR2 features differential clock inputs (CK and CK#). This differential clock is used to capture command and address, the nominal length is related to the address/command group.
Differential clocks lines should be routed to achieve the target differential impedance. Routing signals differentially reduces the flight time of the clocks compared to the single-ended signals. DDR2 design guides recommend that this clock signal be routed at the same length or slightly longer than the address, control and command signals to compensate for this single-ended / differential timing variation.
Source EET Asia:
DRR2 - Get it Right the First Time
Recommended sequence for routing the DDR2 memory:
1. Route data
2. Route address/command
3. Route control
4. Route clocks
5. Route feedback
The data group is routed first because it operates at twice the clock speed and its signal integrity is the highest priority. The data group represents the largest number of traces within the memory bus and has the strictest trace matching requirements.
The address, command and control lines have a relationship to the clock. The effective clock length needs to equal to the longest route within this group.
The designer should perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied.
Source Freescale AN2910:
Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces
DDR2 Differential Clock
DDR2 features differential clock inputs (CK and CK#). This differential clock is used to capture command and address, the nominal length is related to the address/command group.
Differential clocks lines should be routed to achieve the target differential impedance. Routing signals differentially reduces the flight time of the clocks compared to the single-ended signals. DDR2 design guides recommend that this clock signal be routed at the same length or slightly longer than the address, control and command signals to compensate for this single-ended / differential timing variation.
Source EET Asia:
DRR2 - Get it Right the First Time
Thursday, January 10, 2013
Tuesday, January 8, 2013
Altium Designer » DbLib Limits - Best Practices Altium Forum
Altium Forum - Lounge: Altium Live Login in Required
Thursday, January 3, 2013
Creating Silkscreen from 3D Model Data
Mike Kanigan's work flow for creating silkscreen for complex parts using 3D models.
Start with a blank PCB, place the step model, create a board line using a surface of the step file "Board Shape -> Define from 3D Body" feature
Create Primitives From Board Shape -> Change layer to Top Overlay. Copy the new silkscreen outline to the PCBLIB part.
And there you have it!
The nice thing about doing it this way is that it also places pads and PCB cutouts!
I have also used this same technique to generate keepouts from step file enclosures that I then turn into silkscreen so its visible on the PCB.
Link: (Altium Live Account Required)
http://forum.live.altium.com/#posts/195462
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