Collisions

When working with RF Designs Collisions are a way of life.

What we have here is two parts on three pads. Actually it's two parts with overlapping pads.

Only one of the two overlapping parts will be installed at any given time.

This technique is used to minimize parasitic traces and pads (no RF stubs).  

Using this technique you can create controlled impedance routes with minimum impedance discontinuities.

To get through the Design Rule Checks (DRCs) we can either disable the check or create an exception in the rules for the overlapping parts.

I recommend solution number 2 shown below..

Solutions:

1) Disabling Component Clearance Checks (not recommended).

2) Creating a rule with exceptions for the overlapping parts. (recommended).

click on images to view


Syntax:

InComponent('C307') 

Driving Fabrication Outputs using a Variant

Driving Fabrication Outputs using a Variant | Online Documentation for Altium Products:

"This ability is an enhancement to the way in which variants can be used, it allows you to vary a fabrication output. Although it is fabrication output that is being changed, it is only changing the silkscreen output based on a variation in the component's Comment parameter. You can not change any other aspect of the fabricated board, such as the routing, the layout of the components, or the layer stack."

'via Blog this'

3D Extruded Shape Not Updating from Library

The Problem:

Below is an example of a component which does not match the part in the Library and Altium does NOT detect the difference.

Here's the part on the PCB.

Here is the part in the Library

As shown I have added a polarity mark in the 3D body using a small white triangle.

Also the part appears in the Libraries Panel with the polarity mark shown.

However selecting the Component and updating from Libraries finds NO differences.

No Differences Found

Apparently finding differences does not include extruded shapes in a 3D Body.

The Workaround:

Open the footprint *.PCBLIB file then using the PCB Library Panel Update the PCB with the footprint.

Problem Solved:

That's it

DFM - Broken Net

Here's an interesting Broken Net error reported by a fabricator using an ODB++ file generated by Altium.



The DRC checks in Altium found NO opens (Broken Nets)

Examining Net_C401-1 shows where the problem lies: 

As shown above NetC401-1 is passing across the pad of a capacitor, however there is not a connection dot in the pad.

To fix this problem we need to create separate connecting segments along the net to each pad.

There are no checks currently built into in Altium to find this reported error.

DFM - Non Plated Hole - Soldermask FHS + 10mil

Design for Manufacturability (DFM) for Non Plated Thru Hole (NPTH) the soldermask opening should be finished hole size (FHS) + 10mils.

Example: NPTH for test fixture tooling, soldermask = FHS + 10mil (0.25mm)

In Altium this means the Soldermask expansion should be +5mils (0.125mm).

You should also include a copper keep out on all layers of FHS + 10mils.

There are no Design rules or DRCs in Altium for Non-Plated Thru Holes that will catch this DFM issue.

DFM - Soldermask Coverage

There are no design rules in Altium to identify the soldermask coverage problem described below. 

Note the soldermask shown below is too close to a different net. Standard soldermask registration accuracy is +/- 3mils (75um).

You need to use fabrication CAM tools to identify these errors or set your copper to copper rules with clearances that account for soldermask registration accuracy.

Source: High Volume Overseas Contract Manufacturer.

"Soldermask alignment capability exposes traces and features."

"Bridging during the assembly process may occur if the circuit features that pass close to pads are not fully covered by soldermask or potential corrosion problem if lack of coverage exposes copper."

Suggested Solution from Contract Manufacturer:

"Move the circuit features away from the pad or move the pad away from the circuit features. And if the soldermask clearance is large enough then reduce the soldermask clearance. If all of them can not be modified, soldermask encroach on pad should be allowed in lieu of allowing exposed copper feature."

My Comments and Solutions:

The DFM tolerance in the CAM tool for this violation was 2.953mil.  

In Altium the minimum copper to copper clearance for 'ALL'  different nets was 0.15mm (5.905mil). And the soldermask swell was set for 4mils. so the math works out to:

5.095 minus 4 = 1.905  (Copper to Copper minus Soldermask Swell = Coverage)

Copper to Copper Rule minus soldermask swell = soldermask coverage with perfect soldermask registration.

However the soldermask registration accuracy (+/- 3mil) needs to be considered for the outer layers which are covered with soldermask. 

To allow for soldermask registration accuracy of +/- 3mil we would need a minimum copper to copper clearance rule of 7mil.

7 minus 4 = 3mils (Copper to Copper minus Soldermask Swell = Coverage).

For standard LPI soldermask processes the copper to copper rules for the outer layers should be set to least 7mils, preferably 8mils.

For fine pitch parts with pin to pin clearances equal to or less than the minimum copper to copper rule clearance you can gang the soldermask and create rooms with appropriate clearance rules.

That's It.

DFM - Laminate Slivers

"In PCB fabrication process, a copper sliver can cause material to detach during photo-imaging processes in fabrication. Floating pieces can cause defects and shorts which reduce yield. In electric performance aspect, slivers can even contribute to inconsistent impedance if they exist on a plane layer."

Source: High Volume Overseas Contract Manufacturer


My Comments: 

Where is the sliver?  I only see is a small gap in a copper poured plane or polygon.

To understand this DFM error you have to consider the copper photo-imaging process tolerances.

There are no DFM checks in Altium to identify copper laminate slivers, you need to use fabrication CAM and DFM tools to locate these laminate slivers in your designs.

The minimum gap allowed is 4mils.