InPolygon
InNamedPolygon('L3 - 3V3')
(ObjectKind = 'Poly') And (Name like '*L05_GND*')
(OnLayer('L1 TOP') and InPolygon)
(OnLayer('L1 - TOP'))
Not( OnLayer('L8 3V3/RF') OR OnLayer('L9 5V'))
InNetClass('CPW')
InNet('RF_PORT') AND InComponent('X100')
InNet('26MHz')
(InNet('RF_PORT') AND OnLayer('L1 - TOP'))
HasPad('J1400-1') OR HasPad('J1001-1')
InComponent('D1200')
Not (InComponent('TH100') Or InComponent('TH101'))
(OnLayer('L1 TOP') and InPolygon)
(OnLayer('L1 - TOP'))
Not( OnLayer('L8 3V3/RF') OR OnLayer('L9 5V'))
InNetClass('CPW')
InNet('RF_PORT') AND InComponent('X100')
InNet('26MHz')
(InNet('RF_PORT') AND OnLayer('L1 - TOP'))
HasPad('J1400-1') OR HasPad('J1001-1')
InComponent('D1200')
Not (InComponent('TH100') Or InComponent('TH101'))
(ObjectKind = '3D Body') And (Identifier = 'SOM')
(AsMils(HoleDiameter) = 130)
(AsMils(HoleDiameter) >= 8)
WithinRoom('DDR3_ROOM')
OnLayer('L1 TOP') or OnLayer('L16 BOT')
IsPad
IsVia
Hole to Hole Clearance Rules
Thru-Hole Pin
IsThruPin
InPolygon
8mil
NPTH Rules
((HoleDiameter >= PadXSize_AllLayers ) OR (HoleDiameter >= PadYSize_AllLayers))
(HoleDiameter > 0) And (PadIsPlated = 'False')
Routing Rules
Width
InNetClass('DDR_AC') or InNetClass('DDR_DQ')
(ObjectKind = 'Track') And (Layer = 'L11-SIG') and InNetClass('MCP_ADDR[7..30]')
Differential Pair Rules
InNetClass('diff_80')
InNetClass('diff_100') AND NOT withinroom('FPGA_ROOM')
Component Clearance Rules
OnMechanical
InComponent('C1911')
NOT InComponent('R1900') and NOT InComponent('C1904')
InComponentClass ('Class_Name')
Hole to Hole Rules
InNet('GND')
to
InNet('GND')
(AsMils(HoleDiameter) = 130)
(AsMils(HoleDiameter) >= 8)
WithinRoom('DDR3_ROOM')
OnLayer('L1 TOP') or OnLayer('L16 BOT')
IsPad
IsVia
Hole to Hole Clearance Rules
Thru-Hole Pin
IsThruPin
InPolygon
8mil
NPTH Rules
((HoleDiameter >= PadXSize_AllLayers ) OR (HoleDiameter >= PadYSize_AllLayers))
(HoleDiameter > 0) And (PadIsPlated = 'False')
Routing Rules
Width
InNetClass('DDR_AC') or InNetClass('DDR_DQ')
(ObjectKind = 'Track') And (Layer = 'L11-SIG') and InNetClass('MCP_ADDR[7..30]')
Differential Pair Rules
InNetClass('diff_80')
InNetClass('diff_100') AND NOT withinroom('FPGA_ROOM')
Component Clearance Rules
OnMechanical
InComponent('C1911')
NOT InComponent('R1900') and NOT InComponent('C1904')
InComponentClass ('Class_Name')
Hole to Hole Rules
InNet('GND')
to
InNet('GND')
Slots
HoleType = 'Slot'
Net Antennae Rules
To Allow a Net Antennae
NOT (InNet('DXN_0_N') OR InNet('DXP_0_P'))
InNet('NetF1100_1') and IsViolation
Pads
InPadClass('Mtg_Holes')
(HoleDiameter > 0) And (PadIsPlated = 'False')
Check Solder Mask from Hole Edge
5mil
SMD Pads to Thru-Hole Solder
Net Antennae Rules
To Allow a Net Antennae
NOT (InNet('DXN_0_N') OR InNet('DXP_0_P'))
InNet('NetF1100_1') and IsViolation
Pads
InPadClass('Mtg_Holes')
(ObjectKind = 'Pad') And (Component = 'U2')
Soldermask Rules
Tent (Cover) Vias
isVia and AsMils (HoleSize < 15)
NPTH
Soldermask Rules
Tent (Cover) Vias
isVia and AsMils (HoleSize < 15)
NPTH
(HoleDiameter > 0) And (PadIsPlated = 'False')
Check Solder Mask from Hole Edge
5mil
SMD Pads to Thru-Hole Solder
Find Vias In Pads and use Via soldermask encroachment.
Steps:
Identify Vias in Pads using a DRC check.
IsPad
IsVia
AnyNet
Minimum clearance 3mils
Select Components and Unlock Primitives.
Use PCB Filter isVia and HasViolations
Set selected Vias to unique hole size i.e. 8,01 or 10.1mils and use rule based soldermask.
Delete or disable the temporary DRC to find the Vias in Pads
Create a Solder mask expansion Rule for the unique drill hole sized vias.
IsVia AND (AsMils(HoleDiameter) = 8.01)
Check Solder Mask From The Hole Edge
Set expansion i.e. 3 or 4 mils
Done !
That's it !
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