I imported a PADs ASCII V5 file using AD16.0.6
Poured the polygons and ran the DRC checks.
I ran into a few issues (500+). As expected, imports rarely go smoothly in any CAD tool.
The good news is that the majority of the DRCs are related to silkscreen and soldermask violations which can easily be fixed.
The vias came in un-tented (no soldermask) and caused a some DRC violations for soldermask to soldermask clearances. An easy to fix problem.
Fix: Tent VIAs.
For now, I will disable the batch mode for Manufacturing Rules (silkscreen and soldermask).
I'm more interested in the copper to copper violations.
Ignoring the Manufacturing Rules, I'm looking at a measly 154 violations.
Many of these violations are nonsensical same net violations.
For Example:
Same Net Only check for Via and Surface Mount Pad.
There are numerous instances in the design were GND VIAS are in direct contact with PADs that also have GND Nets. So this rule is obviously bogus.
Another bogus rule was: Same Net Via to Via.
Another bogus rule: Max length of a routed net.
Fix: Delete Bogus Rules
On layer 2 of this 4 layer board there are lot GND VIAs with tracks routed from GND VIA to GND VIA.
That's little interesting considering the same layer is also flooded with a GND polygon pour.
Same Layer (L2) with the polygons poured reveals the via to via tracks on layer 2 are not actually needed.
If left in the design these useless tracks will end up in the Gerber data.
Fix: Delete the useless GND tracks on Layer flooded with copper.
Note these GND tracks on layer 2 may have been in the original PADs data. When time permits I plan to review the design in PADs to better understand the source of these anomalies.
An interesting violation occurred where a copper region was found under a QFN.
click on image to view
Close up look
Six signal vias are shorted to solid copper (keepout) region under a QFN package.
The Region came in with different nets making contact with the Region.
Regions are dumb copper objects, unlike polygons which are smart copper.
The pink border and the checked Keepout box provided some insight for the purpose of the region.
This keepout should have came in as polygon cutout, vice a solid region.
Fix: Change the top layer keepout region to a top layer polygon cutout.
Select the Region > Right click > Properties > Change Kind to Polygon Cutout.
Pour the polygons and check the copper area under the QFN.
Fixing the keep out under the QFN resolved 115 of the 154 violations.
Only 2 warnings and 7 violations left, disregarding the silkscreen and soldermask.
I was making good progress cleaning up the the DRC violations, when AD16.0.6 suddenly closed and all of my work was lost. (nothing in the history folder)
It should be easier the second time around, since finding the problems and coming up with solutions is more than half of the battle.
Here we go again . . . practice makes perfect :-)
I opened up the *.pcbDoc which the Import Wizard generated and started working my way back through the fixes for the second time.
This time I'll remember to save the *.PcbDoc often, like after every fix that is implemented.
After applying all of the fixes shown above and saving my work :) I'm ready to knock out those last 2 warnings and 7 copper violations.
The last 7 violations
Region to PAD and Region to Track Clearance Violations
This gold finger edge connector has pads with copper to copper clearances of 9.252mil.
So, the 18mil clearance rule for Region to SMD Pad is not logical. And the 18mil Region to Track rule is not logical.
Fix: Modify Clearances Rules for Region to SMT Pad and Track.
The last 3 violations are due to the pads of a footprint being to close to a keepout that follows the board outline.
An RF End Launch SMA (J1) was placed close to the board edge and keepout.
It is not uncommon to find this violation in RF designs, because RF engineers don't won't to have a discontinuity in the RF path at the board edge.
Fabricators will point out that bare copper will be exposed on the board edge after routing the boards from the panel.
Fabricators typically request that the customer wavier the exposed copper or recommend that the copper be pulled back at least 10 mils from the board edge.
I could not find a rule to use to create an exception for this DRC.
Workarounds are need to resolve this DRC.
One option is the edit the keep out track as shown below.
Or it can be fixed using board clearance for the pullback in place of the keep out trace.
Note the Board Outline Clearance rule was introduced in AD15.
You can use both or either of these fixes in AD15 and higher.
To maintain backward compatibility with older versions of Altium edit the keepout track.
There were two warnings related to Non Plated Through Holes (NPTH).
At the lower and upper left corners of the board there were SMT pads that should have been interpreted as Non Plated Through Holes.
Looking at the pad properties
There were conflicting properties in the imported pad. Top layer and a drilled hole size of 55.118mil.
Fix : Change Layer From Top to Multi-Layer and re-pour the polygons.
The design is now DRC clean except for silkscreen and soldermask, which can easily be fixed.
Summary:
Porting designs between CAD tools always involves fixing a few problems.
Actually it was kinda fun, I like to solve problems.
Every CAD tool I have used occasionally crashes. Altium was able to reproduce and fix the crash that occurred after running DRC checks in this imported design.
Altium is diligently working to reduce crashes and improve stability.
That's It !
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