An experienced Altium user solved this problem using FILLs applied to the soldermask layer as shown below. The result is soldermask squares that tented the VIAs.
Single layer mode - 3D View of the Soldermask
| 1 | Board Outline | |
| 2 | Assy Dwg Top Ref | |
| 3 | Assy Dwg Bot Ref | |
| 4 | Component Outlines | |
| 5 | Board Dimensions | |
| 6 | 3D Bodies | |
| 7 | Fab Drawing Text | |
| 8 | Assy Dwg Top Text | |
| 9 | Assy Dwg Bot Text | |
| 10 | Panel Drawing | |
| 11 | Panel Dimensions | |
| 12 | PCB Scoring/Routing | |
| 13 | Mechanical 13 | |
| 14 | Drill Drawing Text | |
| 15 | Component Courtyards | |
| 16 | Page Frame Top | |
| 17 | Page Frame Bot | |
| 18 | Mechanical 18 | |
| 19 | Mechanical 19 | |
| 20 | Test Points Top | |
| 21 | Test Points Bot | |
| 22 | Mechanical 22 | |
| 23 | Mechanical 23 | |
| 24 | Outlines Layer Pair | |
| 25 | Courtyards Layer Pair | |
| 26 | Mechanical 26 | |
| 27 | Mechanical 27 | |
| 28 | Mechanical 28 | |
| 29 | Mechanical 29 | |
| 30 | Mechanical 30 | |
| 31 | Mechanical 31 | |
| 32 | Mechanical 32 |